This invention relates generally to semiconductor memories and, particularly, to flash memories.
Flash memories typically use a one transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Commonly flash memory is provided in densities that come in standard multiples of a given density. For example, flash memory may be provided in multiples of 32 megabits. Some users may prefer to have an interim density or a density between two successive multiples, such as 48 megabits.
Flash memories generally come in either top boot or bottom boot configurations. The parameters utilized for the booting process in a bottom boot configuration are allocated to the lowest addressable addresses of the flash array. In the top boot configuration, those parameters are allocated to the highest addressable addresses.
To enable an interim density, normally bottom boot flash is utilized. In such case, the interim density may be easily implemented by disabling or locking a memory block (or blocks) associated with the highest (or higher) addressable addresses. In this way, the locked block(s) do not in any way interfere with access to the booting parameters that are stored in the lowest addressable addresses.
A problem arises in providing interim densities with top boot flash memories since the boot parameters are located in precisely the same blocks that would be disabled, normally, to produce the interim density.
Thus, there is a need for a way to enable interim densities in top boot flash memories.